EPM7128AELC84-5

high-density, high-performance device, QFP, –0.5 to 4.6 V, –25 to 25 mA, High-performance

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PartNumber:: EPM7128AELC84-5

Brand:: Altera Corporation - ALTR | Pack: QFP | D/C: 03+

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Products Upload time: 2011-11-09

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Product Summary

The EPM7128AELC84-5 is a high-density, high-performance device based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7128AELC84-5 operates with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz.

Parametrics

EPM7128AELC84-5 absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –0.5 to 4.6 V; (2)VI, DC input voltage: –2.0 to 5.75 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature No bias: –65 to 150℃; (5)TA, Ambient temperature Under bias: –65 to 135℃; (6)TJ, Junction temperature BGA, FineLine BGA, PQFP, and TQFP packages, under bias: 135℃.

Features

EPM7128AELC84-5 features: (1)High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX)architecture; (2)3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability; (3)MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532; (4)EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532; (5)Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1; (6)Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71; (7)Enhanced ISP features ; (8)Enhanced ISP algorithm for faster programming; (9)ISP_Done bit to ensure complete programming; (10)Pull-up resistor on I/O pins during in-system programming; (11)Pin-compatible with the popular 5.0-V MAX 7000S devices; (12)High-density PLDs ranging from 600 to 10,000 usable gates; (13)Extended temperature range.