EP20K600EFC672-2X

Product Summary

The EP20K600EFC672-2X is an FPGA. It is designed with the MultiCore architecture, which combines the strengths of LUT-based and product-term-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, register-intensive, mathematical, or digital signal processing (DSP) designs. The EP20K600EFC672-2X is reconfigurable and is 100% tested prior to shipment. As a result, test vectors do not have to be generated for fault coverage purposes. The EP20K600EFC672-2X is configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller.

Parametrics

EP20K600EFC672-2X absolute maximum ratings: (1)Supply voltage With respect to ground:-0.5 to 3.6V,-0.5 to 4.6V; (2)DC input voltage:-2.0 to 5.75 V; (3)DC output current, per pin:–25 to 25 mA; (4)Storage temperature:–65 to 150℃; (5)Ambient temperature:–65 to 135℃; (6)Junction temperature:135℃.

Features

EP20K600EFC672-2X features: (1)Support for high-speed external memories, including DDR SDRAM and ZBT SRAM (ZBT is a trademark of Integrated Device Technology, Inc.); (2)Bidirectional I/O performance (tCO + tSU) up to 250 MHz; (3)LVDS performance up to 840 Mbits per channel; (4)Direct connection from I/O pins to local interconnect providing fast tCO and tSU times for complex logic; (5)MultiVolt I/O interface support to interface with 1.8-V, 2.5-V, ; (6)3.3-V, and 5.0-V devices; (7)Programmable clamp to VCCIO; (8)Individual tri-state output enable control for each pin; (9)Programmable output slew-rate control to reduce switching noise; (10)Built-in low-skew clock tree; (11)Up to eight global clock signals; (12)ClockLock feature reducing clock delay and skew ClockBoost; (13)feature providing clock multiplication and division; (14)ClockShiftTM programmable clock phase and delay shifting; (15)1.8-V and 2.5-V supply voltage; (16)MultiVoltTM I/O interface support to interface with 1.8-V, 2.5-V, 3.3-V, and 5.0-V devices; (17)ESB offering programmable power-saving mode.

Diagrams