Product Summary

The EP1S40F780C5N is a stratix device. The EP1S40F780C5N is based on a 1.5-V, 0.13μm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. The EP1S40F780C5N offers up to 22 digital signal processing (DSP) blocks with up to 176 embedded multipliers, optimized for DSP applications of the EP1S40F780C5N that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution of the EP1S40F780C5N with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).

Parametrics

EP1S40F780C5N absolute maximum ratings: (1)VCCINT Supply voltage With respect to ground: –0.5 2.4 V; (2)VCCIO: –0.5 4.6 V; (3)VI DC input voltage: –0.5 4.6 V; (4)IOUT DC output current, per pin: –25 40 mA; (5)TSTG Storage temperature No bias: –65 150 ℃; (6)TJ Junction temperature BGA packages under bias: 135 ℃.

Features

EP1S40F780C5N features: (1)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (2)TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers; (3)High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters; (4)Up to 16 global clocks with 22 clocking resources per device region; (5)Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting.

Diagrams

EP1S40F780C5N Stratix LAB Structure

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(USD)
Quantity
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