EP1K100QC208-1

Product Summary

The EP1K100QC208-1 is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks: a configuration controller and a flash memory. The EP1K100QC208-1 is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete.

Parametrics

EP1K100QC208-1 absolute maximum ratings: (1)VCC Supply voltage With respect to ground: -0.2 to 4.6 V; (2)VI DC input voltage With respect to ground: -0.5 to 3.6 V; (3)IMAX DC VCC or ground current: 100 mA; (4)IOUT DC output current, per pin: -25 to 25 mA; (5)PD Power dissipation: 360 mW; (6)TSTG Storage temperature No bias: -65 to 150 ℃; (7)TAMB Ambient temperature Under bias: -65 to 135 ℃; (8)TJ Junction temperature Under bias: 135 ℃.

Features

EP1K100QC208-1 features: (1)Standard flash die and a controller die combined into single stacked chip package; (2)External flash interface supports parallel programming of flash and external processor access to unused portions of memory; (3)Flash memory block/sector protection capability via external flash interface; (4)Supported in EPC16 and EPC4 devices; (5)Page mode support for remote and local reconfiguration with up to eight configurations for the entire system; (6)Compatible with Stratix series Remote System Configuration feature; (7)Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle; (8)Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs; (9)Pin-selectable 2-ms or 100-ms power-on reset (POR) time; (10)Supply voltage of 3.3 V (core and I/O); (11)Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification; (12)Supports ISP via Jam Standard Test and Programming Language (STAPL); (13)Supports JTAG boundary scan; (14)nINIT_CONF pin allows private JTAG instruction to start FPGA configuration; (15)Internal pull-up resistor on nINIT_CONF always enabled; (16)User programmable weak internal pull-up resistors on nCS and OE pins; (17)Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines; (18)Standby mode with reduced power consumption.

Diagrams