EPF6016AQC208

Product Summary

The EPF6016AQC208 is a programmable logic device (PLD). It provides a low-cost alternative to high-volume gate array designs. The EPF6016AQC208 is based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. It has reconfigurable SRAM elements, which give designers the flexibility to quickly change their designs during prototyping and design testing. The EPF6016AQC208 is reprogrammable, and it is 100% tested prior to shipment. It is configured on the board for the specific functionality required.

Parametrics

EPF6016AQC208 absolute maximum ratings: (1)VCC, Supply voltage: –2.0 to 7.0 V With respect to ground; (2)VI, DC input voltage: –2.0 to 7.0 V With respect to ground; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature No bias: –65 to 150℃; (5)TAMB, Ambient temperature Under bias: –65 to 135℃; (6)TJ, Junction temperature PQFP, TQFP, and BGA packages: 135℃.

Features

EPF6016AQC208 features: (1)Register-rich, look-up table- (LUT-) based architecture; (2)OptiFLEX architecture that increases device area efficiency; (3)Typical gates ranging from 5,000 to 24,000 gates; (4)Built-in low-skew clock distribution tree; (5)100% functional testing of all devices; test vectors or scan chains are not required; (6)In-circuit reconfigurability (ICR) via external configuration device or intelligent controller; (7)5.0-V devices are fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2; (8)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic; (9)MultiVolt TM I/O interface operation, allowing a device to bridge between systems operating at different voltages; (10)Low power consumption (typical specification less than 0.5 mA in standby mode) ; (11)3.3-V devices support hot-socketing.

Diagrams