(China (Mainland))
Product Summary
The EP1S40F1020C5 contains a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). The EP1S40F1020C5 provides dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs.
Parametrics
EP1S40F1020C5 absolute maximum ratings: (1)VCCINT Supply voltage: -0.5 to 2.4 V; (2)VCCIO: -0.5 to 4.6 V; (3)VI DC input voltage (3): -0.5 to 4.6 V; (4)IOUT DC output current, per pin: -25 to 40 mA; (5)TSTG Storage temperature No bias: -65 to 150 ℃; (6)TJ Junction temperature BGA packages under bias: 135 ℃.
Features
EP1S40F1020C5 features: (1)10,570 to 79,040 LEs; (2)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (3)TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO); (4)buffers; (5)High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-ccumulate functions, and finite impulse response (FIR) filters; (6)Up to 16 global clocks with 22 clocking resources per device region; (7)Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices; (8)Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices; (9)Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices; (10)Support for remote configuration updates.
Diagrams
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 EP1S40F1020C5 |
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IC STRATIX FPGA 40K LE 1020-FBGA |
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EP1S40F1020C5N |
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IC STRATIX FPGA 40K LE 1020-FBGA |
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